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Si4320
DQD
The Data Quality Detector monitors the I/Q output of the
baseband amplifier chain by counting the consecutive correct 0-
>1, 1->0 transitions. The DQD output indicates the quality of the
signal to be demodulated. Using this method it is possible to
"forecast" the probability of BER degradation. The programmable
DQD parameter defines the threshold for signaling the good/bad
data quality by the digital one-bit DQD output. In cases when the
deviation is close to the bitrate, there should be four transitions
during a single one bit period in the I/Q signals. As the bitrate
decreases in comparison to the deviation, more and more
transitions will happen during a bitperiod.
AFC
By using an integrated Automatic Frequency Control (AFC)
feature, the receiver can synchronize its local oscillator to the
received signal, allowing the use of:
? inexpensive, low accuracy crystals
Event Handling
In order to minimize current consumption, the receiver supports
the sleep mode. Active mode can be initiated by several wake-up
events (wake-up timer timeout, low supply voltage detection, on-
chip FIFO filled up or receiving a request through the serial
interface).
If any wake-up event occurs, the wake-up logic generates an
interrupt signal, which can be used to wake up the
microcontroller, effectively reducing the period the
microcontroller has to be active. The cause of the interrupt can
be read out from the receiver by the microcontroller through the
SDO pin.
Interface and Controller
An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
bandwidth of the baseband signal path. Division ratio for the
microcontroller clock, wake-up timer period, and low supply
?
?
narrower receiver bandwidth (i.e. increased sensitivity)
higher data rate
voltage detector threshold are also programmable. Any of these
auxiliary functions can be disabled when not needed. All
parameters are set to default after power-on; the programmed
Crystal Oscillator
The chip has a single-pin crystal oscillator circuit, which provides
a 10 MHz reference signal for the PLL. To reduce external parts
and simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal
can be found later in this datasheet. The receiver can supply the
clock signal for the microcontroller, so accurate timing is possible
without the need for a second crystal.
When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the Configuration Setting
Command, the chip provides a fixed number (128) of further
clock pulses (“clock tail”) for the microcontroller to let it go to idle
or sleep mode.
Low Battery Voltage Detector
The low battery detector circuit monitors the supply voltage and
generates an interrupt if it falls below a programmable threshold
level. The detector circuit has 50 mV hysteresis.
Wake-Up Timer
The wake-up timer has very low current consumption (1.5 μA
typical) and can be programmed from 1 ms to several days with
an accuracy of ±10%.
values are retained during sleep mode. The interface supports
the read-out of a status register, providing detailed information
about the status of the receiver and the received data. It is also
possible to store the received data bits into the 16bit RX FIFO
register and read them out in a buffered mode. FIFO mode can
be enabled through the SPI compatible interface by setting the fe
bit to 1 in the Output and FIFO Mode Command.
Standalone Operation Mode
The chip also provides a standalone mode, which allows the use
of the receiver without a microcontroller. This mode can be
selected by connecting the CLK/LPDM pin to either VDD or VSS.
After power on, the chip will check this pin. If it is connected to
any supply voltage, then the chip will go to standalone mode.
Otherwise, it will go to microcontroller mode and the pin will
become an output and provide a clock signal for the
microcontroller. To prevent the Si4320 from accidentally entering
a standalone mode, the stray capacitance should be kept below
50 pF on pin 8.
In this mode operating parameters can be selected from a
limited set by “programming” the receiver over its pins. The chip
is addressable and four digital output pins can be controlled by
the received data. Selecting the Low Power Duty-Cycle Mode
(LPDM) the chip consumes less than 0.5 mA average current.
It calibrates itself to the crystal oscillator at every startup. When
the crystal oscillator is switched off, the calibration circuit
switches it back on only long enough for a quick calibration (a
few milliseconds) to facilitate accurate wake-up timing.
3
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